A Processing Element for a Digital Asynchronous/synchronous Vision Chip
نویسندگان
چکیده
This paper presents a new processing cell circuit, suitable for use in massively parallel fine-grain processor arrays, oriented towards image processing applications. The design, based on dynamic logic, is efficient for both local and global operations. In this paper we discuss design trade-offs and provide detailed description of the architecture. A cellular processor array based on the presented design can operate in both discreteand continuous-time domains. Asynchronous execution of global operations significantly increases overall performance. Simulation results indicate the performance in the range from 1.1 (unsigned products) to 2900 (asynchronous binary processing) MOPS/cell.
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